1. Technology Field
The invention relates to a clock and data recovery circuit. Particularly, the invention relates to a clock and data recovery circuit capable of generating a reference clock signal based on a received input data stream.
2. Description of Related Art
FIG. 1 is a structural diagram of a conventional clock and data recovery (CDR) circuit. The clock and data recovery circuit 100 includes a coarse-tuning module 110 and a fine-tuning module 120. The coarse-tuning module 110 is used for providing a coarse-tuning control voltage to the fine-tuning module 120, and the fine-tuning module 120 receives an input data stream IN_DATA, and outputs a data-recovery clock CDR_CLK.
The coarse-tuning module 110 has a crystal oscillator 111, a phase frequency detector 112, a first low-pass filter 113, a first voltage-controlled oscillator 114 and a frequency divider 115. The crystal oscillator 111 generates a reference clock SREF through crystal oscillation. The phase frequency detector 112 compares a phase of the reference clock SREF and a phase of a frequency-divided signal C4, and outputs a control signal C1 according to the comparison result. The first low-pass filter 113 filters the control signal C1 to output a control voltage C2. The first voltage-controlled oscillator 114 oscillates to generate an oscillation signal C3 according to the control voltage C2. The frequency divider 115 divides a frequency of the oscillation signal C3 and outputs the frequency-divided signal C4.
The fine-tuning module 120 has a phase detector 121, a second low-pass filter 122 and a second voltage-controlled oscillator 123. The phase detector 121 compares phases and frequencies of the input data stream IN_DATA and the data-recovery clock CDR_CLK, and outputs a control signal C5 according to the comparison result. The second low-pass filter 122 filters the control signal C5 to output a control voltage C6. After being processed by a resistor R and a capacitor C, the control voltage C2 output by the first low-pass filter 113 is converted into a control voltage C7. The second voltage-controlled oscillator 123 oscillates to generate the data-recovery clock CDR_CLK according to the control voltage C6 and the control voltage C7. The data-recovery lock CDR_CLK is transmitted to the phase detector 121.
The clock and data recovery circuit 100 recovers the input data stream IN_DATA according to the data-recovery clock CDR_CLK, so as to generate a retimed data stream. In some specific specifications, in order to ensure correctness of data recovered by the clock and data recovery circuit 100, jitter of the retimed data stream cannot be too large. Therefore, an error between a frequency of the reference clock SREF generated by the crystal oscillator 111 and a frequency of the input data stream IN_DATA has to be within a specific range. Taking a universal serial bus (USB) 3.0 as an example, the error between the frequency of the reference clock SREF and the frequency of the input data stream IN_DATA has to be smaller than 300 ppm (one ppm is equal to one of a million). Although a commercial crystal oscillator can generate a clock signal with a frequency error smaller than ±100 ppm to serve as an ideal clock signal source, such crystal oscillator is expensive and occupies a large circuit board space.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.